Presentation 2003/12/11
A thought in a search for very high-speed, low-power and ultra high-performance data-driven system architecture. : A system with no system-clock, no system-bus and no central controls
Hiroaki TERADA,
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Abstract(in English) An attempt in seek for a very high-speed, low-power consumption and ultra-high performance integrated system on a chip that resulted in a novel system structure having no system clocks, no passive system buses and no centralised system controls is illustrated .The scheme deploys a self-timed super-pipeline structure that minimizes wiring length uniformly over a chip and thus gives system designers a guarantee that any system with minimum power consumption is autonomously generated. It is also shown that the self-timed pipeline structure shows an interesting functionality by utilizing inherent localized controllability, which cannot be realisable with, conventional synchronously clocked scheme.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) data-driven processing / super-pipeline / self-timed data transfer / multiprocessing
Paper # ICD2003-189(2003-12)
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Conference Date 2003/12/11(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) A thought in a search for very high-speed, low-power and ultra high-performance data-driven system architecture. : A system with no system-clock, no system-bus and no central controls
Sub Title (in English)
Keyword(1) data-driven processing
Keyword(2) super-pipeline
Keyword(3) self-timed data transfer
Keyword(4) multiprocessing
1st Author's Name Hiroaki TERADA
1st Author's Affiliation Kochi University of Technology:Information and Communication Labs, Japan Telecom Corp()
Date 2003/12/11
Paper # ICD2003-189(2003-12)
Volume (vol) vol.103
Number (no) 509
Page pp.pp.-
#Pages 6
Date of Issue