| Presentation | 2003/12/11 JPEG2000 Encoder VLSI Architecture for High Definition Movie Yoshikazu GYOBU, Yosuke OKAIRI, Masashi MIYAZAKI, Toshiyuki TANIUCHI, Masahide UMEZU, Tsutomu EDA, Toshiyuki KATO, Masahiro FUKUI, Tsuyoshi FUJINO, Hironori YAMAUCHI, Yukihiro NAKAMURA, Sadayasu ONO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Standardization of digital cinema has been progressed adopting the ultra high-definition images with 8 million pixels as well as using JPEG2000 compression technologies. The images will be applied not only to digitize cinema industries but to provide live events with highest quality. The key to realize this system is to drastically reinvent the video CODEC to be much smaller in size. While presuming to use the 65-90 nm technologies that would be now realized, the possible single chip video ENCODER architecture was studied in this paper. Especially, among many studies, we had proposed various methods to decrease the size of working memory, and we concluded that it is basically possible to reinvent the ENCODER into a single chip system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Digital Cinema / MOTION-JPEG2000 / Real-time Encoder / SoC / 90nm-process |
| Paper # | ICD2003-188(2003-12) |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/12/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | JPEG2000 Encoder VLSI Architecture for High Definition Movie |
| Sub Title (in English) | |
| Keyword(1) | Digital Cinema |
| Keyword(2) | MOTION-JPEG2000 |
| Keyword(3) | Real-time Encoder |
| Keyword(4) | SoC |
| Keyword(5) | 90nm-process |
| 1st Author's Name | Yoshikazu GYOBU |
| 1st Author's Affiliation | VLSI center, Ritsumeikan University() |
| 2nd Author's Name | Yosuke OKAIRI |
| 2nd Author's Affiliation | VLSI center, Ritsumeikan University |
| 3rd Author's Name | Masashi MIYAZAKI |
| 3rd Author's Affiliation | VLSI center, Ritsumeikan University |
| 4th Author's Name | Toshiyuki TANIUCHI |
| 4th Author's Affiliation | VLSI center, Ritsumeikan University |
| 5th Author's Name | Masahide UMEZU |
| 5th Author's Affiliation | VLSI center, Ritsumeikan University |
| 6th Author's Name | Tsutomu EDA |
| 6th Author's Affiliation | VLSI center, Ritsumeikan University |
| 7th Author's Name | Toshiyuki KATO |
| 7th Author's Affiliation | VLSI center, Ritsumeikan University |
| 8th Author's Name | Masahiro FUKUI |
| 8th Author's Affiliation | VLSI center, Ritsumeikan University |
| 9th Author's Name | Tsuyoshi FUJINO |
| 9th Author's Affiliation | VLSI center, Ritsumeikan University |
| 10th Author's Name | Hironori YAMAUCHI |
| 10th Author's Affiliation | VLSI center, Ritsumeikan University |
| 11th Author's Name | Yukihiro NAKAMURA |
| 11th Author's Affiliation | Electronics and Communication, Kyoto University |
| 12th Author's Name | Sadayasu ONO |
| 12th Author's Affiliation | Media and Governance, Keio University |
| Date | 2003/12/11 |
| Paper # | ICD2003-188(2003-12) |
| Volume (vol) | vol.103 |
| Number (no) | 509 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |