Presentation 2003/12/11
Evaluation of a low power operation machine which used the variable number of pipeline stages
Seiichi URUSHIYAMA, Jubei TADA, Gensuke GOTO,
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Abstract(in English) Recently, power consumption of a processor increases as improving the performance. On the other hand, a high-performance and low-power consumption processor is required for a personal digital assistant. For reducing power consumption of pipeline registers, we propose a pipeline which number of pipeline stages can be changed. We designed and evaluated a 32-bit multiplier which adopted variable number of pipeline stages. The proposed pipeline was able to reduce power-delay product consumption compared with a traditional pipeline.
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Keyword(in English) variable number of pipeline stages / power consumption / power-delay product
Paper # ICD2003-186(2003-12)
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Conference Date 2003/12/11(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of a low power operation machine which used the variable number of pipeline stages
Sub Title (in English)
Keyword(1) variable number of pipeline stages
Keyword(2) power consumption
Keyword(3) power-delay product
1st Author's Name Seiichi URUSHIYAMA
1st Author's Affiliation Graduate School of Science and Engineering, The University of Yamagata()
2nd Author's Name Jubei TADA
2nd Author's Affiliation Graduate School of Science and Engineering, The University of Yamagata
3rd Author's Name Gensuke GOTO
3rd Author's Affiliation Graduate School of Science and Engineering, The University of Yamagata
Date 2003/12/11
Paper # ICD2003-186(2003-12)
Volume (vol) vol.103
Number (no) 509
Page pp.pp.-
#Pages 5
Date of Issue