| Presentation | 2003/9/5 1V-Operation 630MHz Frequency. Divider Circuits Yasuko YAMAMOTO, Toshimasa MATSUOKA, Kenji TANIGUCHI, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This report presents the 630MHz frequency divider circuits with 0.35μm standard CMOS process which operates at 1V supply voltage. Source Coupled Logic topology and NAND combined D-Flip Flop are effective in terms of low voltage operation and low power consumption as compared with True Single Phase Clock counterparts. The frequency divider achieves the power consumption of 2.1mW. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Frequency divider / Low Power / Low Voltage Operation / Source Coupled Logic / D-Flip Flop |
| Paper # | ICD2003-103 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2003/9/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 1V-Operation 630MHz Frequency. Divider Circuits |
| Sub Title (in English) | |
| Keyword(1) | Frequency divider |
| Keyword(2) | Low Power |
| Keyword(3) | Low Voltage Operation |
| Keyword(4) | Source Coupled Logic |
| Keyword(5) | D-Flip Flop |
| 1st Author's Name | Yasuko YAMAMOTO |
| 1st Author's Affiliation | Department of Electronics and Information Systems, Osaka University : Advanced Technologies Fusion Laboratory, Matsushita Electric Works, Ltd.() |
| 2nd Author's Name | Toshimasa MATSUOKA |
| 2nd Author's Affiliation | Department of Electronics and Information Systems, Osaka University |
| 3rd Author's Name | Kenji TANIGUCHI |
| 3rd Author's Affiliation | Department of Electronics and Information Systems, Osaka University |
| Date | 2003/9/5 |
| Paper # | ICD2003-103 |
| Volume (vol) | vol.103 |
| Number (no) | 299 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |