Presentation 2003/9/5
A Design of a Compact 2GHz-PLL with New Adaptive Active Loop Filter Circuit
Shiro Dosho, Masaomi Toyama, Naoshi Yanagisawa,
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Abstract(in English) This paper describes the design of new active low pass filter for Phase-Locked-Loop (PLL) with adaptive biasing technique. Using new low pass filter, the PLL can automatically adjust the loop bandwidth and damping factor to the frequency of reference clock. Moreover, new LPF can decrease the capacitance value to 1/10 of conventional one. Test chip of 2GHz-PLL was fabricated in 0.15um CMOS Process.
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Keyword(in English) Phase-Locked-Loops / Active Filter / Adaptive Bias / Miniaturization / CMOS
Paper # ICD2003-97
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Committee ICD
Conference Date 2003/9/5(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Design of a Compact 2GHz-PLL with New Adaptive Active Loop Filter Circuit
Sub Title (in English)
Keyword(1) Phase-Locked-Loops
Keyword(2) Active Filter
Keyword(3) Adaptive Bias
Keyword(4) Miniaturization
Keyword(5) CMOS
1st Author's Name Shiro Dosho
1st Author's Affiliation System LSI Technology Development Center Corporate Development Division, Semiconductor Company Matsushita Electric Industrial Co.Ltd.()
2nd Author's Name Masaomi Toyama
2nd Author's Affiliation System LSI Technology Development Center Corporate Development Division, Semiconductor Company Matsushita Electric Industrial Co.Ltd.
3rd Author's Name Naoshi Yanagisawa
3rd Author's Affiliation System LSI Technology Development Center Corporate Development Division, Semiconductor Company Matsushita Electric Industrial Co.Ltd.
Date 2003/9/5
Paper # ICD2003-97
Volume (vol) vol.103
Number (no) 299
Page pp.pp.-
#Pages 6
Date of Issue