Presentation	2003/9/5 Small Area D/A Converter Using Weighted Mean Sample-and-Hold Circuits Masayuki UNO, Shoji KAWAHITO,
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Abstract(in English)	Offset free D/A converters suitable for multiple channel integration such as DAC array are proposed. A 4-bit Sub-DAC is based on a sample-and-hold circuit together with some capacitors for weighted mean calculation. A higher resolution D/A converter can be realized by combining two or more sub-DAC. Since this sub-DAC is constructed less number of capacitors, power dissipation caused of charging or discharging capacitors can be minimized, and chip area can be reduced. This paper also proposes the design of a sample-and-hold circuit having class AB output stage that hold D/A output voltage during reset phase and drives capacitive load efficiently.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	D/A Converter / Sample and Hold circuits / Weighted Means / Class AB
Paper #	ICD2003-93
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Conference Information
Committee	ICD
Conference Date	2003/9/5(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Small Area D/A Converter Using Weighted Mean Sample-and-Hold Circuits
Sub Title (in English)
Keyword(1)	D/A Converter
Keyword(2)	Sample and Hold circuits
Keyword(3)	Weighted Means
Keyword(4)	Class AB
1st Author's Name	Masayuki UNO
1st Author's Affiliation	Shizuoka University()
2nd Author's Name	Shoji KAWAHITO
2nd Author's Affiliation	Research Institute of Electronics, Shizuoka University
Date	2003/9/5
Paper #	ICD2003-93
Volume (vol)	vol.103
Number (no)	299
Page	pp.pp.-
#Pages	6
Date of Issue