Presentation	2003/9/4 A 1Obit 120MSample/s Low-Power Parallel Pipeline A/D Converter Daisuke MIYAZAKI, Masanori FURUTA, Shoji KAWAHITO,
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Abstract(in English)	This paper describes a low-power high-speed parallel pipeline ADC. The thorough use of digital calibration and the pseudo-differential pipeline ADC architecture allow to realize the low-power design of high-speed ADC's. Capacitor mismatch, gain and offset errors are measured by a technique using INL plot, without any modification to ADC core. A prototype ADC with the error correction logic is fabricated in 0.3 μm 2-poly 3-metal CMOS technology. The 1Obit 120M Sample/s ADC achieves 0.14LSB of DNL and 0.8LSB of INL with very low-power dissipation of 75mW at 2V.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Pipelined A/D Converter / Low-Power / High-Speed
Paper #	ICD2003-89
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Conference Information
Committee	ICD
Conference Date	2003/9/4(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A 1Obit 120MSample/s Low-Power Parallel Pipeline A/D Converter
Sub Title (in English)
Keyword(1)	Pipelined A/D Converter
Keyword(2)	Low-Power
Keyword(3)	High-Speed
1st Author's Name	Daisuke MIYAZAKI
1st Author's Affiliation	Research Institute of Electronics, Shizuoka University()
2nd Author's Name	Masanori FURUTA
2nd Author's Affiliation	Graduate School of Electronic Science and Technology
3rd Author's Name	Shoji KAWAHITO
3rd Author's Affiliation	Research Institute of Electronics, Shizuoka University
Date	2003/9/4
Paper #	ICD2003-89
Volume (vol)	vol.103
Number (no)	298
Page	pp.pp.-
#Pages	6
Date of Issue