Presentation	2003/8/14 A Development of Low Power SoC at STARC Koichiro Ishibashi, Tetsuya Fujimoto, Hiroyuki Okada, Takahiro Yamashita,
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Abstract(in English)	Low power SoC technology, which realizes ubiquitous computing era, is investigated. Low voltage operdion of 0.5V for logic and memory IPs and 1.0V operation for analog IP are target techniques. Such low voltage logic, memory and analog IPs are to be implemented in a single chip to realize super low power SoC. We have developed Self-Adjusted Forward Body Bias Technique to achieve low voltage operation of logic circuit, V-driver circuit to reduce power of bus, and high speed ADC which includes compensation circuit of device fluctuation.
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Paper #	SDM2003-127,ICD2003-60
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Committee	ICD
Conference Date	2003/8/14(1days)
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Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
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Title (in English)	A Development of Low Power SoC at STARC
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1st Author's Name	Koichiro Ishibashi
1st Author's Affiliation	Semiconductor Academic Research Center(STARC)()
2nd Author's Name	Tetsuya Fujimoto
2nd Author's Affiliation	Semiconductor Academic Research Center(STARC)
3rd Author's Name	Hiroyuki Okada
3rd Author's Affiliation	Semiconductor Academic Research Center(STARC)
4th Author's Name	Takahiro Yamashita
4th Author's Affiliation	Semiconductor Academic Research Center(STARC)
Date	2003/8/14
Paper #	SDM2003-127,ICD2003-60
Volume (vol)	vol.103
Number (no)	261
Page	pp.pp.-
#Pages	6
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