| Presentation | 2003/8/14 A Wide Range 1.0V-3.6V 200Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors Takahiro SHIMADA, Hiromi NOTANI, Yasunobu NAKASE, Hiroshi MAKINO, Shuhei IWADE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We proposed a push-pull output buffer that maintains the data transmission rate for lower supply voltages. It operates at an internal supply voltage (VDD) of 0.7-1.6 V and an interface supply voltage (VDDX) of 1.0-3.6 V. In low VDDX operation, the output buffer utilizes parasitic bipolar transistors instead of MOS transistors to maintain drivability. Furthermore forward body bias control is provided for the level converter in low VDD operation. We fabricated a test chip with a standard 0.15mm CMOS process. Measurement results indicate that the proposed output buffer achieves 200 Mbps operation at VDD of 0.7 V and VDDX of 1.0 V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low Power / I-O / parasitic bipolar transistor / forward bias |
| Paper # | SDM2003-125,ICD2003-58 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/8/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Wide Range 1.0V-3.6V 200Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors |
| Sub Title (in English) | |
| Keyword(1) | Low Power |
| Keyword(2) | I-O |
| Keyword(3) | parasitic bipolar transistor |
| Keyword(4) | forward bias |
| 1st Author's Name | Takahiro SHIMADA |
| 1st Author's Affiliation | LSI Product Technology Unit, Renesas Technology Corporation() |
| 2nd Author's Name | Hiromi NOTANI |
| 2nd Author's Affiliation | LSI Product Technology Unit, Renesas Technology Corporation |
| 3rd Author's Name | Yasunobu NAKASE |
| 3rd Author's Affiliation | LSI Product Technology Unit, Renesas Technology Corporation |
| 4th Author's Name | Hiroshi MAKINO |
| 4th Author's Affiliation | LSI Product Technology Unit, Renesas Technology Corporation |
| 5th Author's Name | Shuhei IWADE |
| 5th Author's Affiliation | Osaka Institute of Technology |
| Date | 2003/8/14 |
| Paper # | SDM2003-125,ICD2003-58 |
| Volume (vol) | vol.103 |
| Number (no) | 261 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |