Presentation 2003/8/14
A Floating-Gate-MOS-Based Low-Power CDMA Matched Filter Employing Capacitance Disconnection Technique
Toshihiko YAMASAKI, Tomohiro FUKUDA, Tadashi SHIBATA,
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Abstract(in English) Low-power and compact CDMA matched filters have been developed based on the floating-gate MOS technology. The low-power operation has been achieved by employing the single-step matching scheme and disconnecting the coupling-capacitors unnecessary for the matching operation. The 255-chip matched filter fabricated in a 0.35-μm technology demonstrated 6mW operation at 3V power supply and the chip rate of 5MS/s, while occupying the chip area of 1.0 mm^2.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Floating-Gate MOS / Neuron-MOS / CDMA / Matched Filter
Paper # SDM2003-124,ICD2003-57
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Committee ICD
Conference Date 2003/8/14(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Floating-Gate-MOS-Based Low-Power CDMA Matched Filter Employing Capacitance Disconnection Technique
Sub Title (in English)
Keyword(1) Floating-Gate MOS
Keyword(2) Neuron-MOS
Keyword(3) CDMA
Keyword(4) Matched Filter
1st Author's Name Toshihiko YAMASAKI
1st Author's Affiliation Department of Electronic Engineering, School of Engineering, The University of Tokyo()
2nd Author's Name Tomohiro FUKUDA
2nd Author's Affiliation Department of Electronic Engineering, School of Engineering, The University of Tokyo
3rd Author's Name Tadashi SHIBATA
3rd Author's Affiliation Department of Frontier Informatics, School of Frontier Science, The University of Tokyo
Date 2003/8/14
Paper # SDM2003-124,ICD2003-57
Volume (vol) vol.103
Number (no) 261
Page pp.pp.-
#Pages 6
Date of Issue