| Presentation | 2003/8/14 Static CMOS Pair Logic Gate with Degraded Input Capacitance Keisuke MURAYA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For designing CMOS circuit, a load capacitance is required to be small and driving current(Ids) is required to be large for fast propergation. A width of transistor is regarding to the capacitance and the Ids. In a logic gate, a width of the driving transistor cannot be eliminated due to keep the Ids. But, off-state transistor width can be degraded to reduce load capacitance for the before stage. However, the eliminated transistor cannot drive the after stage rapidly when it's turned on. Then, we studied a method of using this gate with this eliminated tarnsistor. One conventional logic gate is duplicated and reduced the width of P-MOSFET or N-MOSFET for each. And, a pair of these logic gates are used as complemental for fast switching. This paper deals with this pair logic gate to apply entair of circuit. A converting method of conventional logic gate, a catalogue of basic logic gates, a connecting circuit among pair logic and conventional circuit, and a result of simultaion are presented. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS / Static Circuit / Gate Capacitance / Delay / Pair Logic Gate |
| Paper # | SDM2003-123,ICD2003-56 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/8/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Static CMOS Pair Logic Gate with Degraded Input Capacitance |
| Sub Title (in English) | |
| Keyword(1) | CMOS |
| Keyword(2) | Static Circuit |
| Keyword(3) | Gate Capacitance |
| Keyword(4) | Delay |
| Keyword(5) | Pair Logic Gate |
| 1st Author's Name | Keisuke MURAYA |
| 1st Author's Affiliation | FUJITSU Co.Ltd() |
| Date | 2003/8/14 |
| Paper # | SDM2003-123,ICD2003-56 |
| Volume (vol) | vol.103 |
| Number (no) | 261 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |