Presentation	2003/8/14 Study of Threthold Voltage Fluctuation of FD-SOI MOSFETs Yoshiyuki SHIMIZU, Toshimasa MATSUOKA, Kenji TANIGUCHI,
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Abstract(in English)	We have investigated the threshold voltage of FD(Fully-Depleted) SOI(Silicon on Insulator) devices. Although large, MOSFETs with Floating body structure show a large fluctuation in threshold voltage at saturation bias condtions. In order to study physical mechanisms behind the threshold voltage fluctuations, we measured a threshold voltage of 50 type of MOSFETs laied-out on a chip with different gate sizes(L=0.2-1.8um, W=0.9-9.0um) and different body structures, 255 MOSFETs for each size.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	FD-SOI / Floating-Body structure / threshold voltage
Paper #	SDM2003-119,ICD2003-52
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Committee	ICD
Conference Date	2003/8/14(1days)
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Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Study of Threthold Voltage Fluctuation of FD-SOI MOSFETs
Sub Title (in English)
Keyword(1)	FD-SOI
Keyword(2)	Floating-Body structure
Keyword(3)	threshold voltage
1st Author's Name	Yoshiyuki SHIMIZU
1st Author's Affiliation	Graduate School of Engineering, Osaka University()
2nd Author's Name	Toshimasa MATSUOKA
2nd Author's Affiliation	Graduate School of Engineering, Osaka University
3rd Author's Name	Kenji TANIGUCHI
3rd Author's Affiliation	Graduate School of Engineering, Osaka University
Date	2003/8/14
Paper #	SDM2003-119,ICD2003-52
Volume (vol)	vol.103
Number (no)	261
Page	pp.pp.-
#Pages	5
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