Presentation	2003/7/17 A Low Leakage Power Digital Circuit Scheme for Digital Appliance : Zigzag SCCMOS Scheme Takayuki MIYAZAKI, Kyeong-Sik MIN, Hiroshi KAWAGUCHI, Takayasu SAKURAI,
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Abstract(in English)	Zigzag Super Cut-off CMOS is proposed as clock-gating replacement in deep sub-micron era. The proposed scheme is applicable in V_ less than 1-V, since it uses only low threshold voltage transistor in power switches. By inserting the power switches in zigzag, the serially connected transistors in power switch of Super Cut-off CMOS is avoided without any overstresses. Wake-up time of less than 1/3 the clock cycle and three-orders-of-magnitude leakage current reduction are confirmed. A method for switching the higher-man-V_ and lower-than-VSs voltage is proposed. Furthermore, it is shown that the proposed scheme is applicable to a selector circuit.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Low Leakage / Clock-gating / Active leakage
Paper #	ICD2003-39
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Conference Information
Committee	ICD
Conference Date	2003/7/17(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Low Leakage Power Digital Circuit Scheme for Digital Appliance : Zigzag SCCMOS Scheme
Sub Title (in English)
Keyword(1)	Low Leakage
Keyword(2)	Clock-gating
Keyword(3)	Active leakage
1st Author's Name	Takayuki MIYAZAKI
1st Author's Affiliation	Institute of Industrial Science, University of Tokyo()
2nd Author's Name	Kyeong-Sik MIN
2nd Author's Affiliation	Institute of Industrial Science, University of Tokyo
3rd Author's Name	Hiroshi KAWAGUCHI
3rd Author's Affiliation	Institute of Industrial Science, University of Tokyo
4th Author's Name	Takayasu SAKURAI
4th Author's Affiliation	Institute of Industrial Science, University of Tokyo
Date	2003/7/17
Paper #	ICD2003-39
Volume (vol)	vol.103
Number (no)	216
Page	pp.pp.-
#Pages	6
Date of Issue