| Presentation | 2002/5/17 One-chip Receiver IC for 622Mb/s Optical Communication Systems Torn TAKESHITA, Takashi NISHIMURA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An optical receiver IC for 622Mb/s which integrates a trans-impedance amplifier, a post amplifier and a clock recovery is developed using BiCMOS process. The one-chip receiver achieves a wide dynamic range sensitivity from -29.4 to 0dBm with a isolation technique. A novel phase-locked loop (PLL) circuit without reference-clock has a high tolerance for input with duty cycle distortion from 70 to 130 %. The characteristics conform to ITU standard. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Optical Communication Systems / One-chip / Double-guard / Duty Cycle Distortion / PLL Circuit |
| Paper # | ICD2002-26 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2002/5/17(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | One-chip Receiver IC for 622Mb/s Optical Communication Systems |
| Sub Title (in English) | |
| Keyword(1) | Optical Communication Systems |
| Keyword(2) | One-chip |
| Keyword(3) | Double-guard |
| Keyword(4) | Duty Cycle Distortion |
| Keyword(5) | PLL Circuit |
| 1st Author's Name | Torn TAKESHITA |
| 1st Author's Affiliation | Semiconductor Network Company, SONY Corporation() |
| 2nd Author's Name | Takashi NISHIMURA |
| 2nd Author's Affiliation | Semiconductor Network Company, SONY Corporation |
| Date | 2002/5/17 |
| Paper # | ICD2002-26 |
| Volume (vol) | vol.102 |
| Number (no) | 83 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |