Presentation 2002/5/16
A Single-Chip MPEG-2 Codec Based on Customizable Media Microprocessor
Shuji Michinaka, Shunichi Ishiwata, Tomoo Yamakage, Yoshiro Tsuboi, Takayoshi Shimazawa, Tomoko Kitazawa, Kunihiko Yahagi, Hideki Takeda, Akihiro Oue, Tomoya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, Goichi Ootomo, Masataka Matsui,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on 72 mm^2 die, is described. It has heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as VLIW one and DSP one inherent in its architecture. Making full use of the extensions, the chip executes video, audio and system encoding and decoding concurrently in real time.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) MPEG2 MP@ML codec / heterogeneous multiprocessor architecture / customizable microprocessor architecture / media microprocessor / hardware and software development tool
Paper # ICD2002-20
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Conference Date 2002/5/16(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Single-Chip MPEG-2 Codec Based on Customizable Media Microprocessor
Sub Title (in English)
Keyword(1) MPEG2 MP@ML codec
Keyword(2) heterogeneous multiprocessor architecture
Keyword(3) customizable microprocessor architecture
Keyword(4) media microprocessor
Keyword(5) hardware and software development tool
1st Author's Name Shuji Michinaka
1st Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation()
2nd Author's Name Shunichi Ishiwata
2nd Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
3rd Author's Name Tomoo Yamakage
3rd Author's Affiliation Research and Development Center, Toshiba Corporation
4th Author's Name Yoshiro Tsuboi
4th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
5th Author's Name Takayoshi Shimazawa
5th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
6th Author's Name Tomoko Kitazawa
6th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
7th Author's Name Kunihiko Yahagi
7th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
8th Author's Name Hideki Takeda
8th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
9th Author's Name Akihiro Oue
9th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
10th Author's Name Tomoya Kodama
10th Author's Affiliation Research and Development Center, Toshiba Corporation
11th Author's Name Nobu Matsumoto
11th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
12th Author's Name Takayuki Kamei
12th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
13th Author's Name Takashi Miyamori
13th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
14th Author's Name Goichi Ootomo
14th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
15th Author's Name Masataka Matsui
15th Author's Affiliation SoC Reseach & Development Center, Semiconductor Company, Toshiba Corporation
Date 2002/5/16
Paper # ICD2002-20
Volume (vol) vol.102
Number (no) 82
Page pp.pp.-
#Pages 6
Date of Issue