| Presentation | 2002/5/16 Two Channel HDTV Video decode processor Shigeyuki OKADA, Kazuhiko TAKETA, Yuh MATSUDA, Tugio MORI, Tsuyoshi WATANABE, Shin'ichiro OKADA, Yoshifumi MATSUSHITA, Hideki YAMAUCHI, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | HDTV video processor capable handling decoding and displaying two MPEG MP@HL streams simultasneously has been developed. High throughput pipelining technique, efficient parallel data bus structure and adoption of cooperative processing architecture with hardware and software using application specific DSPs are proposed. By employing these techniques, high performance video processor with small hardware size and low power dissipation are realized. Proposed parallel pipeline technique has achieved two times higher throughput than conventional single pipelining. The parallel data bus configuration can improve data transfer efficiency dramatically and reduce required operating frequency. A cooperative operation for MPEG2 decoding using software with application specific DSP and dedicated hardware can achieve both high performance and small hardware size. This single chip video processor is manufactured of 0.18μm five-layer metal CMOS process and the chip size is 6.86mm × 6.86mm. The power consumption is 0.8 W when the supply voltage is 1 .8V and operating frequency is 135 MHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | MPEG2 / SOC / digital TV / Image compression / Multimedia |
| Paper # | ICD2002-19 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2002/5/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Two Channel HDTV Video decode processor |
| Sub Title (in English) | |
| Keyword(1) | MPEG2 |
| Keyword(2) | SOC |
| Keyword(3) | digital TV |
| Keyword(4) | Image compression |
| Keyword(5) | Multimedia |
| 1st Author's Name | Shigeyuki OKADA |
| 1st Author's Affiliation | Material and Device Research center, SANYO Electric co., Ltd.() |
| 2nd Author's Name | Kazuhiko TAKETA |
| 2nd Author's Affiliation | Material and Device Research center, SANYO Electric co., Ltd. |
| 3rd Author's Name | Yuh MATSUDA |
| 3rd Author's Affiliation | Material and Device Research center, SANYO Electric co., Ltd. |
| 4th Author's Name | Tugio MORI |
| 4th Author's Affiliation | Material and Device Research center, SANYO Electric co., Ltd. |
| 5th Author's Name | Tsuyoshi WATANABE |
| 5th Author's Affiliation | Material and Device Research center, SANYO Electric co., Ltd. |
| 6th Author's Name | Shin'ichiro OKADA |
| 6th Author's Affiliation | Material and Device Research center, SANYO Electric co., Ltd. |
| 7th Author's Name | Yoshifumi MATSUSHITA |
| 7th Author's Affiliation | Material and Device Research center, SANYO Electric co., Ltd. |
| 8th Author's Name | Hideki YAMAUCHI |
| 8th Author's Affiliation | Material and Device Research center, SANYO Electric co., Ltd. |
| Date | 2002/5/16 |
| Paper # | ICD2002-19 |
| Volume (vol) | vol.102 |
| Number (no) | 82 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |