Presentation | 2002/5/16 A Design of Vision Chip Architecture for Higher order Auto-correlation Kenkichi YAMAMOTO, Idaku ISHII, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | For high-speed moving objects, much faster vision system than video signal is necessary. Vision chip on which sensors and parallel processing elements are integrated is fast and real-time vision system for sub milli-second image processing. Such vision chips are categorized in two types ; 1) programmable vision chip for general purpose, 2) vision chip integrated specific algorithm for high resolution. In this paper, we propose a special purpose vision chip architecture on which higher order auto-correlation and moment algorithms are integrated. And we report our developing prototype chip based on time vision chip architecture. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | high speed real-time vision / massively parallel processing / integrated architecture / CMOS sensor |
Paper # | ICD2002-18 |
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Committee | ICD |
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Conference Date | 2002/5/16(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A Design of Vision Chip Architecture for Higher order Auto-correlation |
Sub Title (in English) | |
Keyword(1) | high speed real-time vision |
Keyword(2) | massively parallel processing |
Keyword(3) | integrated architecture |
Keyword(4) | CMOS sensor |
1st Author's Name | Kenkichi YAMAMOTO |
1st Author's Affiliation | Faculty of Engineering, Tokyo University of Agriculture and Technology() |
2nd Author's Name | Idaku ISHII |
2nd Author's Affiliation | Faculty of Engineering, Tokyo University of Agriculture and Technology |
Date | 2002/5/16 |
Paper # | ICD2002-18 |
Volume (vol) | vol.102 |
Number (no) | 82 |
Page | pp.pp.- |
#Pages | 6 |
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