Presentation 2002/5/16
FPGA Prototyping of Low-Power CPU with Gated Clock Control
Teppei HIROTSU, Kotaro SHIMAMURA, Ryo FUJITA, Tatsuya TOCHIO, Motostugu FUJII,
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Abstract(in English) FPGA Prototyping is an efficient way to shorten the development time of an embedded system. But we can't apply this method to the embedded system including low-power CPU, because it is difficult to synthesize a low-power CPU to FPGA. We develop the way to synthesize a low-power CPU to FPGA using auto-generation of gated clocks and distribution of module stand-by signals. A large scale hardware description of SoC(System on a Chip) including a low-power CPU is automatically divided into some parts and mapped into multi-FPGA device.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / Prototyping / Verification / Low-Power / CPU
Paper # ICD2002-16
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Committee ICD
Conference Date 2002/5/16(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) FPGA Prototyping of Low-Power CPU with Gated Clock Control
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Prototyping
Keyword(3) Verification
Keyword(4) Low-Power
Keyword(5) CPU
1st Author's Name Teppei HIROTSU
1st Author's Affiliation Hitachi Research Lab., Hitachi, Ltd.()
2nd Author's Name Kotaro SHIMAMURA
2nd Author's Affiliation Hitachi Research Lab., Hitachi, Ltd.
3rd Author's Name Ryo FUJITA
3rd Author's Affiliation Hitachi Research Lab., Hitachi, Ltd.
4th Author's Name Tatsuya TOCHIO
4th Author's Affiliation Semiconductor & Integrated Circuits, Hitachi, Ltd.
5th Author's Name Motostugu FUJII
5th Author's Affiliation Semiconductor & Integrated Circuits, Hitachi, Ltd.
Date 2002/5/16
Paper # ICD2002-16
Volume (vol) vol.102
Number (no) 82
Page pp.pp.-
#Pages 6
Date of Issue