| Presentation | 2003/2/27 Design of a Digital Resistive-Fuse Network Circuit for Coarse Image Region Segmentation and Its Implementation Using an FPGA Teppei NAKANO, Takashi MORIE, Hiroshi ANDO, Hideaki ISHIZU, Atsushi IWATA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The resistive-fuse network model was proposed as a model that segments a image in rough and smoothes each segmented region. This paper proposes a digital architecture of this model. In our architecture, the bit accuracy of input images can be lowered by making the bit accuracy in the state updating calculation higher than that of input images. Thus, the total memory capacity can be reduced. By changing the contents of the look-up tables, we can perform other image processing such as edge emphasis. We also show an implementation of the architecture on an FPGA, and describe a PC system using it. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | image processing / region segmentation / edge emphasis / FPGA |
| Paper # | VLD2002-154,ICD2002-219 |
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| Committee | ICD |
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| Conference Date | 2003/2/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of a Digital Resistive-Fuse Network Circuit for Coarse Image Region Segmentation and Its Implementation Using an FPGA |
| Sub Title (in English) | |
| Keyword(1) | image processing |
| Keyword(2) | region segmentation |
| Keyword(3) | edge emphasis |
| Keyword(4) | FPGA |
| 1st Author's Name | Teppei NAKANO |
| 1st Author's Affiliation | Graduate School of Advanced Sciences of Matter, Hiroshima University() |
| 2nd Author's Name | Takashi MORIE |
| 2nd Author's Affiliation | Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology |
| 3rd Author's Name | Hiroshi ANDO |
| 3rd Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 4th Author's Name | Hideaki ISHIZU |
| 4th Author's Affiliation | Hiroshima Perfectural Institute of Science and Technology |
| 5th Author's Name | Atsushi IWATA |
| 5th Author's Affiliation | Graduate School of Advanced Sciences of Matter, Hiroshima University |
| Date | 2003/2/27 |
| Paper # | VLD2002-154,ICD2002-219 |
| Volume (vol) | vol.102 |
| Number (no) | 685 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |