Presentation	2003/2/27 FPGA Speed Improvement mixing Multiple Gate Width Routing Switches Yohei MATSUMOTO, Akira MASAKI,
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Abstract(in English)	The operating speed and packaging density of logic circuits implemented by FPGAs are lower than that of logic circuits implemented by ASICs. Such weak points of FPGAs are almost due to routing switches, therefore its transistor sizing becomes essential. Previous works studied this problem assuming that all the routing switches have uniform gate width. In this work, a new routing architecture is proposed assuming multiple gate widths. Compared with the conventional architecture, critical path delays can be reduced by about 20%.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	FPGA / Routing Switch / Pass Transistor / Elmore Delay
Paper #	VLD2002-153,ICD2002-218
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Conference Information
Committee	ICD
Conference Date	2003/2/27(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	FPGA Speed Improvement mixing Multiple Gate Width Routing Switches
Sub Title (in English)
Keyword(1)	FPGA
Keyword(2)	Routing Switch
Keyword(3)	Pass Transistor
Keyword(4)	Elmore Delay
1st Author's Name	Yohei MATSUMOTO
1st Author's Affiliation	Graduate School of Natural Science and Technology, Okayama University()
2nd Author's Name	Akira MASAKI
2nd Author's Affiliation	Faculty of Engineering, Okayama University
Date	2003/2/27
Paper #	VLD2002-153,ICD2002-218
Volume (vol)	vol.102
Number (no)	685
Page	pp.pp.-
#Pages	6
Date of Issue