| Presentation | 2003/2/27 Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells Ulkuhan Ekiniciel, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The problem of designing VLSI systems is becoming very complex. This complexity can be partially simplified by using PLAs, because of its simplicity, regularity, flexibility, programmability, and predictability. In this paper we propose a module generator, which uses a design constraint to achieve a flexible transistor sizing by a logic cell generation part. And generated logic cells can be easily adapted to layout generator. Almost all of these logic cells have 2-input. 2-input logic cells are implemented in place of conventional AND/OR planes. By using the 2-input logic cells, some classes of logic function can be implemented in a smaller circuit area. Also this module generator has a design rule interface part. With design rule interface part module generator acquires flexibility to process technologies, and module generator becomes adaptable to new process technologies. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Module Generator / Dual-Rail PLA / 2-input Logic Cell / Design Rule Interface / Transistor Sizing |
| Paper # | VLD2002-152,ICD2002-217 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/2/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells |
| Sub Title (in English) | |
| Keyword(1) | Module Generator |
| Keyword(2) | Dual-Rail PLA |
| Keyword(3) | 2-input Logic Cell |
| Keyword(4) | Design Rule Interface |
| Keyword(5) | Transistor Sizing |
| 1st Author's Name | Ulkuhan Ekiniciel |
| 1st Author's Affiliation | Department of Electronic Engineering, The University of Tokyo() |
| 2nd Author's Name | Hiroaki Yamaoka |
| 2nd Author's Affiliation | Department of Electronic Engineering, The University of Tokyo |
| 3rd Author's Name | Makoto Ikeda |
| 3rd Author's Affiliation | Department of Electronic Engineering, The University of Tokyo:VLSI Design and Education Center, The University of Tokyo |
| 4th Author's Name | Kunihiro Asada |
| 4th Author's Affiliation | Department of Electronic Engineering, The University of Tokyo:VLSI Design and Education Center, The University of Tokyo |
| Date | 2003/2/27 |
| Paper # | VLD2002-152,ICD2002-217 |
| Volume (vol) | vol.102 |
| Number (no) | 685 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |