Presentation | 2003/2/27 Quick Noise Estimation Using Multi Terminal F-matrix in Power Grid Model Satoshi SUGIYAMA, Makoto IKEDA, Kunihiro ASADA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | With increasing interconnect densities and lower power supply voltage, power supply noise has become an important factor for deep sub-micron design. Power supply noise increases the signal delay and causes the false switching in the worst case. Therefore the quick power supply noise estimation on VLSI chips has become increasingly important. In this paper, we propose a methodology for estimating noise statically and quickly at all the nodes in a general graph such as power grid model by dividing power grid lines into multi terminal F-matrices and using transfer functions. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Power Supply Noise / Multi Terminal F-matrix / Transfer Function |
Paper # | VLD2002-150,ICD2002-215 |
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Committee | ICD |
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Conference Date | 2003/2/27(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Quick Noise Estimation Using Multi Terminal F-matrix in Power Grid Model |
Sub Title (in English) | |
Keyword(1) | Power Supply Noise |
Keyword(2) | Multi Terminal F-matrix |
Keyword(3) | Transfer Function |
1st Author's Name | Satoshi SUGIYAMA |
1st Author's Affiliation | Department of Electronic Engineering, The University of Tokyo() |
2nd Author's Name | Makoto IKEDA |
2nd Author's Affiliation | VLSI Design and Education Center (VDEC), The University of Tokyo |
3rd Author's Name | Kunihiro ASADA |
3rd Author's Affiliation | VLSI Design and Education Center (VDEC), The University of Tokyo |
Date | 2003/2/27 |
Paper # | VLD2002-150,ICD2002-215 |
Volume (vol) | vol.102 |
Number (no) | 685 |
Page | pp.pp.- |
#Pages | 6 |
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