Presentation | 2003/2/27 HDL Design of ALU based on Constructive Timing Violation Technique and its Evaluation Asami TANINO, Toshinori SATO, Itsujiro ARITA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | It is the situation that wire delay in circuit determines clock frequency of a chip rather than gate delay, with progress of semiconductor process technology. Moreover, freqency of microprocesser continues improving and it is becoming difficult to satisfy timing constraints. In recent years, microprocessers with high performance and low power is increasing importance. In this research, we design Carry Select Adder using Verilog-HDL, and investigate the distribution of timing failures depending on timing constraints, evaluating the usefulness of Constructive Timing Violation Technique. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Timing Constraints / Fault Tolerance / Carry Select Adder / Low Power Design |
Paper # | VLD2002-147,ICD2002-212 |
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Committee | ICD |
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Conference Date | 2003/2/27(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | HDL Design of ALU based on Constructive Timing Violation Technique and its Evaluation |
Sub Title (in English) | |
Keyword(1) | Timing Constraints |
Keyword(2) | Fault Tolerance |
Keyword(3) | Carry Select Adder |
Keyword(4) | Low Power Design |
1st Author's Name | Asami TANINO |
1st Author's Affiliation | KYUSYU INSTITUTE OF TECHNOLOGY() |
2nd Author's Name | Toshinori SATO |
2nd Author's Affiliation | KYUSYU INSTITUTE OF TECHNOLOGY |
3rd Author's Name | Itsujiro ARITA |
3rd Author's Affiliation | KYUSYU INSTITUTE OF TECHNOLOGY |
Date | 2003/2/27 |
Paper # | VLD2002-147,ICD2002-212 |
Volume (vol) | vol.102 |
Number (no) | 685 |
Page | pp.pp.- |
#Pages | 6 |
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