| Presentation | 2003/1/24 Vector Memory Expansion System For The Old Logic Tester Yoshikazu Takahashi, Kazuhiro Yamada, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes a low-cost memory expansion system for the old logic tester series. Using this system, the old tester has the same capability as the latest logic tester. This system will allow the old tester to be used for ASIC wafer testing until 2010. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | T33XX LSSD vector pattern DFT |
| Paper # | CPM2002-155,ICD2002-200 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/1/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Vector Memory Expansion System For The Old Logic Tester |
| Sub Title (in English) | |
| Keyword(1) | T33XX LSSD vector pattern DFT |
| 1st Author's Name | Yoshikazu Takahashi |
| 1st Author's Affiliation | Semiconductor Test Engineering, IBM Japan, Ltd. /() |
| 2nd Author's Name | Kazuhiro Yamada |
| 2nd Author's Affiliation | |
| Date | 2003/1/24 |
| Paper # | CPM2002-155,ICD2002-200 |
| Volume (vol) | vol.102 |
| Number (no) | 623 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |