| Presentation | 2003/1/23 Fault tracing of the SoC by utilizing successive circuit extraction from the layout : Fault tracing of the IP designed in a boundary scan manner Katsuyoshi MIURA, Koji NAKAMAE, Hiromu FUJIOKA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, we propose a fault tracing method of the SoC (system on chip) designed in a boundary scan manner by utilizing successive circuit extraction from the layout. The circuit information is extracted from the layout data after flattening them in order to make the method effective in SoCs designed in various design manners. Only an IP (intellectual property) containing the origin of the fault is flatten to reduce the processing time and memory requirement. The function of the extracted circuit is recognized in order to shorten the time to trace the faulty signals. The wire to be measured is determined by utilizing the extracted circuit information, then a signal waveform on the wire is acquired by an internal diagnosis system such as the electron beam (EB) test system. The faulty signal is traced toward the origin of the fault by comparing the acquircd waveform with the reference waveform. Our method can also treat IPs designed in a boundary scan manner. The binary search is carried out to localize a non stuck-at fault, such as a short fault, on the scan path in the case where the fault is not localized correctly by the conventional method. We simulate the fault tracing of a short fault on the scan path to show validity of our method. Then we discuss the processing time and the amount of used memory of circuit extraction and recognition. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SoC / boundary scan / EB test system / CAD layout data / circuit extraction / circuit recognition |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/1/23(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fault tracing of the SoC by utilizing successive circuit extraction from the layout : Fault tracing of the IP designed in a boundary scan manner |
| Sub Title (in English) | |
| Keyword(1) | SoC |
| Keyword(2) | boundary scan |
| Keyword(3) | EB test system |
| Keyword(4) | CAD layout data |
| Keyword(5) | circuit extraction |
| Keyword(6) | circuit recognition |
| 1st Author's Name | Katsuyoshi MIURA |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Osaka University() |
| 2nd Author's Name | Koji NAKAMAE |
| 2nd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| 3rd Author's Name | Hiromu FUJIOKA |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| Date | 2003/1/23 |
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| Volume (vol) | vol.102 |
| Number (no) | 622 |
| Page | pp.pp.- |
| #Pages | 6 |
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