| Presentation | 2003/1/23 Efficient and High Quality Test Using Deterministic Built-in Test Kazumi HATAYAMA, Michinobu NAKAO, Yoshikazu KIYOSHIGE, Koichiro NATSUME, Yasuo SATO, Takaharu NAGUMO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Conventional scan test approach has a serious problem of increasing test data volume for very large logic LSIs. BIST (Built-in Self Test) is a well-known approach for reducing test data volume drastically. However conventional random BIST approach has a big issue on test quality. Here we propose an approach based on neighborhood pattern generation as deterministic BIST which utilizes high quality test patterns generated by ATPG. Experimental results for industrial circuits illustrate the effectiveness of our approach for efficient and high quality test. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BIST / Neighborhood Pattern / Reseeding / Test Data Reduction / Test Data Compression / Test Quality |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/1/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Efficient and High Quality Test Using Deterministic Built-in Test |
| Sub Title (in English) | |
| Keyword(1) | BIST |
| Keyword(2) | Neighborhood Pattern |
| Keyword(3) | Reseeding |
| Keyword(4) | Test Data Reduction |
| Keyword(5) | Test Data Compression |
| Keyword(6) | Test Quality |
| 1st Author's Name | Kazumi HATAYAMA |
| 1st Author's Affiliation | Semiconductor & Integrated Circuits, Hitachi, Ltd.() |
| 2nd Author's Name | Michinobu NAKAO |
| 2nd Author's Affiliation | Semiconductor & Integrated Circuits, Hitachi, Ltd. |
| 3rd Author's Name | Yoshikazu KIYOSHIGE |
| 3rd Author's Affiliation | Semiconductor & Integrated Circuits, Hitachi, Ltd. |
| 4th Author's Name | Koichiro NATSUME |
| 4th Author's Affiliation | Semiconductor & Integrated Circuits, Hitachi, Ltd. |
| 5th Author's Name | Yasuo SATO |
| 5th Author's Affiliation | Device Development Center, Hitachi, Ltd. |
| 6th Author's Name | Takaharu NAGUMO |
| 6th Author's Affiliation | Enterprise Server Division, Hitachi, Ltd. |
| Date | 2003/1/23 |
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| Volume (vol) | vol.102 |
| Number (no) | 622 |
| Page | pp.pp.- |
| #Pages | 6 |
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