| Presentation | 2003/1/23 Logic BIST Accelerator (LBA) : A Key Device for At-speed Testing of Large System-on-chips Ichiro KOHNO, Yoshio TAKAMINE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A logic BIST accelerator (LBA) enables at-speed testing of large and high-speed system-on-chips by overcoming timing problems during test. It is based on a flexible clock control circuit, a two-phase-clocked BIST controller, and new physical design strategy. It was confirmed that the LBA improves testing speed on a 5.8-million-transistor system-on-chip. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | cost of testing, at-speed logic BIST / timing / clock period / physical design |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2003/1/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Logic BIST Accelerator (LBA) : A Key Device for At-speed Testing of Large System-on-chips |
| Sub Title (in English) | |
| Keyword(1) | cost of testing, at-speed logic BIST |
| Keyword(2) | timing |
| Keyword(3) | clock period |
| Keyword(4) | physical design |
| 1st Author's Name | Ichiro KOHNO |
| 1st Author's Affiliation | Hitachi, Ltd. Semiconductor & Integrated Circuits() |
| 2nd Author's Name | Yoshio TAKAMINE |
| 2nd Author's Affiliation | Hitachi, Ltd. Semiconductor & Integrated Circuits |
| Date | 2003/1/23 |
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| Volume (vol) | vol.102 |
| Number (no) | 622 |
| Page | pp.pp.- |
| #Pages | 6 |
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