| Presentation | 2002/12/13 A 6bit 400Msps 70mW CMOS ADC for a HDD Read Channel Koichi Ono, Junko Ogawa, Motoyasu Yano, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The design of a low power 6bit, 400Msps, 1.8V CMOS ADC is presented. This ADC is based on interpolated parallel architecture in which the transistor sizes are optimized to achieve the required linearity and simultaneously minimize the power consumption. When operated at 400Msps with 1.8/2.4V power supply the ADC dissipates 70mW. The ADC is fabricated in a 0.18um CMOS process. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | ADC / Interpolated Parallel / offset cancel |
| Paper # | ICD2002-181 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2002/12/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 6bit 400Msps 70mW CMOS ADC for a HDD Read Channel |
| Sub Title (in English) | |
| Keyword(1) | ADC |
| Keyword(2) | Interpolated Parallel |
| Keyword(3) | offset cancel |
| 1st Author's Name | Koichi Ono |
| 1st Author's Affiliation | Device & Circuit Development Department, Sony Corp Semiconductor Network Company() |
| 2nd Author's Name | Junko Ogawa |
| 2nd Author's Affiliation | Device & Circuit Development Department, Sony Corp Semiconductor Network Company |
| 3rd Author's Name | Motoyasu Yano |
| 3rd Author's Affiliation | Device & Circuit Development Department, Sony Corp Semiconductor Network Company |
| Date | 2002/12/13 |
| Paper # | ICD2002-181 |
| Volume (vol) | vol.102 |
| Number (no) | 526 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |