| Presentation | 2004/6/24 Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004)) Soon-Young Oh, Jang-Gu Yun, Bin-Feng Huang, Yong-Jin Kim, Hee-Hwan Ji, Ui-Sik Kim, Han-Seob Cha, Sang-Bum Heo, Jeong-Gun Lee, Jin-Suk Wang, Hi-Deok Lee, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A novel NiSi technology with bi-layer Co/TiN structure as a capping layer was proposed for the highly thermal immune Ni Silicide technology. Much better thermal immunity of Ni Silicide was certified up to 700 □, 30 min furnace annealing by introducing Co/TiN bi-layer capping. The proposed structure was successfully applied to the gate layers down to 80 nm and the sheet resistance showed little degradation even after the high temperature furnace annealing of 650 □, 30 min. The Ni/Co/TiN structure is very promising for the nano-scale MOSFET technology which needs the ultra shallow junction and high temperature post silicidation processes. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Ni-Silicide / bi-layer capping / ternary phase / nano-scale MOSFET |
| Paper # | ED2004-82,SDM2004-94 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2004/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Thermally Robust Nickel Silicide Process Technology for Nano-Scale CMOS Technology(Session B5 Si-Devices I)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004)) |
| Sub Title (in English) | |
| Keyword(1) | Ni-Silicide |
| Keyword(2) | bi-layer capping |
| Keyword(3) | ternary phase |
| Keyword(4) | nano-scale MOSFET |
| 1st Author's Name | Soon-Young Oh |
| 1st Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University() |
| 2nd Author's Name | Jang-Gu Yun |
| 2nd Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University |
| 3rd Author's Name | Bin-Feng Huang |
| 3rd Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University |
| 4th Author's Name | Yong-Jin Kim |
| 4th Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University |
| 5th Author's Name | Hee-Hwan Ji |
| 5th Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University |
| 6th Author's Name | Ui-Sik Kim |
| 6th Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University |
| 7th Author's Name | Han-Seob Cha |
| 7th Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University |
| 8th Author's Name | Sang-Bum Heo |
| 8th Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University |
| 9th Author's Name | Jeong-Gun Lee |
| 9th Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University |
| 10th Author's Name | Jin-Suk Wang |
| 10th Author's Affiliation | Dept. of Electronics Engineering, Chungnam National University / |
| 11th Author's Name | Hi-Deok Lee |
| 11th Author's Affiliation | |
| Date | 2004/6/24 |
| Paper # | ED2004-82,SDM2004-94 |
| Volume (vol) | vol.104 |
| Number (no) | 156 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |