AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))

Presentation	2004/6/23 AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004)) Sanghoon Hwang, Minkyu Song,
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Abstract(in English)	A 3V 8-bit 500MSPS CMOS folding/interpolation ADC is proposed. For the purpose of improving SNDR, distributed track-and-hold circuits, a novel analog latch, and digital encoder are proposed. The chip has been fabricated with a 0.35um 2-poly 3-metal CMOS technology. The effective chip area is about 1.2mm × 0.8mm and it dissipates about 210mW at 3V power supply. The INL and DNL are within ± 1LSB, respectively. The SNDR is about 43dB, when input is 50MHz.
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Paper #	ED2004-60,SDM2004-72
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Paper Information
Registration To	Silicon Device and Materials (SDM)
Language	ENG
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	AN 8-BIT 500MSPS CMOS A/D CONVERTER WITH A NOVEL ANALOG DYNAMIC LATCH(Session B2 Si Circuits)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
Sub Title (in English)
Keyword(1)
1st Author's Name	Sanghoon Hwang
1st Author's Affiliation	Dept. of Semiconductor Science, Dongguk University()
2nd Author's Name	Minkyu Song
2nd Author's Affiliation	Dept. of Semiconductor Science, Dongguk University
Date	2004/6/23
Paper #	ED2004-60,SDM2004-72
Volume (vol)	vol.104
Number (no)	155
Page	pp.pp.-
#Pages	4
Date of Issue