| Presentation | 2004/6/14 Low Cost and Highly Reliable, 65nm-node Cu Dual Damascene Interconnects Makoto UEKI, Mitsuru NARIHIRO, Hiroto OHTAKE, Masayoshi TAGAMI, Munehiro TADA, Fuminori ITO, Yoshimichi HARADA, Mari ABE, Naoya INOUE, Koichi ARAI, Tsuneo TAKEUCHI, Shinobu SAITO, Takahiro ONODERA, Naoya FURUTAKE, Masayuki HIROI, Makoto SEKINE, Yoshihiro HAYASHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Fully-scaled-down,65nm-node Cu dual damascene interconnects (DDIs) with 180nm/200nm-pitched lines and 100nm^φ-vias have been developed in full porous-SiOCH films (k=2.5). Two new techniques are introduced such as (1) a low thermal-budget process for securing the DDl via-yield without the Cu agglomeration, and (2) a "DD pore seal" covering all the side walls of the line-trenches and the vias for improving the dielectric reliability. The full porous-SiOCH DDl with the thin Ta/TaN barrier improves the overall RC product by 24% against the porous-on-rigid, hybrid single damascene interconnects (SDIs). The cost-effective, DDls with k_ |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Copper interconnect / porous low-k / dual damascene / pore sealing / low thermal budget process |
| Paper # | SDM2004-36 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2004/6/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low Cost and Highly Reliable, 65nm-node Cu Dual Damascene Interconnects |
| Sub Title (in English) | |
| Keyword(1) | Copper interconnect |
| Keyword(2) | porous low-k |
| Keyword(3) | dual damascene |
| Keyword(4) | pore sealing |
| Keyword(5) | low thermal budget process |
| 1st Author's Name | Makoto UEKI |
| 1st Author's Affiliation | System Devices Research Laboratories, NEC Corporation() |
| 2nd Author's Name | Mitsuru NARIHIRO |
| 2nd Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 3rd Author's Name | Hiroto OHTAKE |
| 3rd Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 4th Author's Name | Masayoshi TAGAMI |
| 4th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 5th Author's Name | Munehiro TADA |
| 5th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 6th Author's Name | Fuminori ITO |
| 6th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 7th Author's Name | Yoshimichi HARADA |
| 7th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 8th Author's Name | Mari ABE |
| 8th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 9th Author's Name | Naoya INOUE |
| 9th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 10th Author's Name | Koichi ARAI |
| 10th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 11th Author's Name | Tsuneo TAKEUCHI |
| 11th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 12th Author's Name | Shinobu SAITO |
| 12th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 13th Author's Name | Takahiro ONODERA |
| 13th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 14th Author's Name | Naoya FURUTAKE |
| 14th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| 15th Author's Name | Masayuki HIROI |
| 15th Author's Affiliation | NEC Electronics Corporation |
| 16th Author's Name | Makoto SEKINE |
| 16th Author's Affiliation | NEC Electronics Corporation |
| 17th Author's Name | Yoshihiro HAYASHI |
| 17th Author's Affiliation | System Devices Research Laboratories, NEC Corporation |
| Date | 2004/6/14 |
| Paper # | SDM2004-36 |
| Volume (vol) | vol.104 |
| Number (no) | 134 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |