| Presentation | 2004/1/23 Room-Temperature Demonstration of Highly-Functional Single-Electron Transistor Logic Based on Quantum Mechanical Effect in Ultra-Small Silicon Dot Masumi SAITOH, Toshiro HIRAMOTO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes the room-temperature (RT) demonstration of new highly-functional single-electron transistor (SET) logic based on the quantum mechanical effect in the ultra-small silicon dot. We fabricate single-hole transistors (SHTs) in the form of extremely constricted channel MOSFETs and observe large Coulomb blockade (CB) oscillations with the peak-to-valley current ratio (PVCR) of 10^2 at RT. In the fabricated single-dot SHTs, clear negative differential conductance (NDC) with the PVCR of 11.8 is also observed at RT because of the large quantum level spacing in the ultra-small dot. By utilizing the observed NDC, XOR operation is successfully demonstrated as a current output in just one SHT. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | single-electron transisotor / single-hole transistor / ultra-small dot / Coulomb blockade oscillations / negative differential conductance / quantum level spacing / resonant tunneling / room temperature operation / single-electron transistor logic / XOR operation |
| Paper # | SDM2003-218 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2004/1/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Room-Temperature Demonstration of Highly-Functional Single-Electron Transistor Logic Based on Quantum Mechanical Effect in Ultra-Small Silicon Dot |
| Sub Title (in English) | |
| Keyword(1) | single-electron transisotor |
| Keyword(2) | single-hole transistor |
| Keyword(3) | ultra-small dot |
| Keyword(4) | Coulomb blockade oscillations |
| Keyword(5) | negative differential conductance |
| Keyword(6) | quantum level spacing |
| Keyword(7) | resonant tunneling |
| Keyword(8) | room temperature operation |
| Keyword(9) | single-electron transistor logic |
| Keyword(10) | XOR operation |
| 1st Author's Name | Masumi SAITOH |
| 1st Author's Affiliation | Institute of Industrial Science, University of Tokyo() |
| 2nd Author's Name | Toshiro HIRAMOTO |
| 2nd Author's Affiliation | Institute of Industrial Science, University of Tokyo |
| Date | 2004/1/23 |
| Paper # | SDM2003-218 |
| Volume (vol) | vol.103 |
| Number (no) | 631 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |