Presentation	2003/8/15 Design Guideline of HfSiON Gate Dielectrics for 65 nm CMOS Generation Takeshi WATANABE, Mariko TAKAYANAGI, Ryosuke IIJIMA, Kazunari ISHIMARU, Yoshitaka TSUNASHIMA, Hidemi ISHIUCHI,
PDF Download Page	PDF download Page Link
Abstract(in Japanese)	(See Japanese page)
Abstract(in English)	Sub-100 nm CMOSFETs with HfSiON gate dielectrics were fabricated and the guideline of Hf concentration (C_) is presented to obtain the superior device performance for the first time. It is found that the drive current is lower than that of SiO_2 in short channel MOSFET. However, MOSFETs with lower C_ results in higher drive current. On the other hand, lower C_ is required for lower the gate leakage current (I_g). Therefore, C_ should be kept low as long as I_g is acceptable in order to obtain good MOSFET performance. It is demonstrated that 50 nm gate CMOSFET with optimized HfSiON show high drive current of 650 μA/um and 250 μA/um for n- and p-MOSFET, respectively, with low I_g of 0.7 A/cm^2. This performance exceeds reported value of sub-100 nm CMOSFET with high-k materials.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	CMOS / HfSiON / high-k / gate dielectrics / Hf concentration
Paper #	SDM2003-145,ICD2003-78
Date of Issue

Conference Information
Committee	SDM
Conference Date	2003/8/15(1days)
Place (in Japanese)	(See Japanese page)
Place (in English)
Topics (in Japanese)	(See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To	Silicon Device and Materials (SDM)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Design Guideline of HfSiON Gate Dielectrics for 65 nm CMOS Generation
Sub Title (in English)
Keyword(1)	CMOS
Keyword(2)	HfSiON
Keyword(3)	high-k
Keyword(4)	gate dielectrics
Keyword(5)	Hf concentration
1st Author's Name	Takeshi WATANABE
1st Author's Affiliation	SoC Research & Development Center, Semiconductor Company()
2nd Author's Name	Mariko TAKAYANAGI
2nd Author's Affiliation	SoC Research & Development Center, Semiconductor Company
3rd Author's Name	Ryosuke IIJIMA
3rd Author's Affiliation	Corporate Research & Development Center, Toshiba Corporation
4th Author's Name	Kazunari ISHIMARU
4th Author's Affiliation	SoC Research & Development Center, Semiconductor Company
5th Author's Name	Yoshitaka TSUNASHIMA
5th Author's Affiliation	Process & Manufacturing Engineering Center, Semiconductor Company
6th Author's Name	Hidemi ISHIUCHI
6th Author's Affiliation	SoC Research & Development Center, Semiconductor Company
Date	2003/8/15
Paper #	SDM2003-145,ICD2003-78
Volume (vol)	vol.103
Number (no)	260
Page	pp.pp.-
#Pages	6
Date of Issue