Presentation 2003/8/15
Bitline/Plateline Reference-Level-Precharge Scheme for High-Density ChainFeRAM
Kohei Oikawa, D. Takashima, S. Shiratake, K. Hoya, H.O. Joachim,
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Abstract(in English) This paper proposes a new bitline/plateline precharge and driving scheme for high-speed and high-density chain FeRAM. Both bitline and plateline are precharged to reference level, and cell data is readout by applying bias to ferroelectric capacitor by pulling up plateline and pulling down bitline in access. This scheme suppresses both reliability degradation of cell transistors and signal-loss inherent to chain FeRAM architecture. Furthermore, this scheme reduces the active power dissipation by 1 0% without access time penalty.
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Keyword(in English) ferroelectric memory / ChainFeRAM / low power
Paper # SDM2003-139,ICD2003-72
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Committee SDM
Conference Date 2003/8/15(1days)
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Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Bitline/Plateline Reference-Level-Precharge Scheme for High-Density ChainFeRAM
Sub Title (in English)
Keyword(1) ferroelectric memory
Keyword(2) ChainFeRAM
Keyword(3) low power
1st Author's Name Kohei Oikawa
1st Author's Affiliation Semiconductor Company, Toshiba Corp.()
2nd Author's Name D. Takashima
2nd Author's Affiliation Semiconductor Company, Toshiba Corp.
3rd Author's Name S. Shiratake
3rd Author's Affiliation Semiconductor Company, Toshiba Corp.
4th Author's Name K. Hoya
4th Author's Affiliation Semiconductor Company, Toshiba Corp.
5th Author's Name H.O. Joachim
5th Author's Affiliation Infineon Technologies Japan K.K.
Date 2003/8/15
Paper # SDM2003-139,ICD2003-72
Volume (vol) vol.103
Number (no) 260
Page pp.pp.-
#Pages 4
Date of Issue