| Presentation | 2003/8/15 The Umbrella Cell : A Logic-Process-Compatible 2T Cell for SOC Applications Satoru AKIYAMA, Nobuhiro OODAIRA, Tsuyoshi ISHIKAWA, Digh HISAMOTO, Takao WATANABE, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose the Umbrella Cell, a logic-process-compatible 2T-DRAM cell for SOC applications. The cell has two logic transistors and a planar MIM capacitor placed on a Cu wire above the transistors to form an umbrella-like structure. This requires one additional photo mask. Its area is 26 F^2, approximately 60% smaller than a 6T cell. Careful bias design and a dual-precharge scheme solve the coupling problems inherent to the cell and allow the use of thin-oxide logic transistors as well as operation at a bit-line voltage of 0.72 V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SOC / Memory cell / Umbrella Cell / Metal-Insulator-Metal Capacitor / Retention time / Dual Precharge Scheme |
| Paper # | SDM2003-138,ICD2003-71 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
|---|---|
| Conference Date | 2003/8/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The Umbrella Cell : A Logic-Process-Compatible 2T Cell for SOC Applications |
| Sub Title (in English) | |
| Keyword(1) | SOC |
| Keyword(2) | Memory cell |
| Keyword(3) | Umbrella Cell |
| Keyword(4) | Metal-Insulator-Metal Capacitor |
| Keyword(5) | Retention time |
| Keyword(6) | Dual Precharge Scheme |
| 1st Author's Name | Satoru AKIYAMA |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| 2nd Author's Name | Nobuhiro OODAIRA |
| 2nd Author's Affiliation | Hitachi ULSI Systems Co., Ltd. |
| 3rd Author's Name | Tsuyoshi ISHIKAWA |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 4th Author's Name | Digh HISAMOTO |
| 4th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 5th Author's Name | Takao WATANABE |
| 5th Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| Date | 2003/8/15 |
| Paper # | SDM2003-138,ICD2003-71 |
| Volume (vol) | vol.103 |
| Number (no) | 260 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |