Presentation 2003/8/15
Development of Low Power Data Recovery Circuit for SFI-5 Interface
Hiroki YAMASHITA, Tatsuya SAITOH, Fumio YUUKI, Akio KOYAMA, Masahito SONEHARA,
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Abstract(in English) We developed a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Our unique approach of treating a sequential 16-bit incoming data as one unit achieved a fully digital "eye-tracking" DR circuit. Fabricated by 0.18-um SiGe-BiCMOS technology, the area of the DR circuit is 0.02-mm^2/ch and its power consumption is 50 mW/ch at 1.8 V. The measured jitter tolerance at 2.5 Gb/s is 0.7 UI p-p, which satisfies the jitter specifications for the SFI-5.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SFI-5 / DR / Interface / Jitter / Digital / SiGe-BiCMOS
Paper # SDM2003-133,ICD2003-66
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Committee SDM
Conference Date 2003/8/15(1days)
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Registration To Silicon Device and Materials (SDM)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of Low Power Data Recovery Circuit for SFI-5 Interface
Sub Title (in English)
Keyword(1) SFI-5
Keyword(2) DR
Keyword(3) Interface
Keyword(4) Jitter
Keyword(5) Digital
Keyword(6) SiGe-BiCMOS
1st Author's Name Hiroki YAMASHITA
1st Author's Affiliation Central Research Laboratory, Hitachi Ltd()
2nd Author's Name Tatsuya SAITOH
2nd Author's Affiliation Central Research Laboratory, Hitachi Ltd
3rd Author's Name Fumio YUUKI
3rd Author's Affiliation Central Research Laboratory, Hitachi Ltd
4th Author's Name Akio KOYAMA
4th Author's Affiliation Device Development Center, Hitachi Ltd
5th Author's Name Masahito SONEHARA
5th Author's Affiliation Device Development Center, Hitachi Ltd
Date 2003/8/15
Paper # SDM2003-133,ICD2003-66
Volume (vol) vol.103
Number (no) 260
Page pp.pp.-
#Pages 6
Date of Issue