| Presentation | 2003/6/23 [Invited]Front-End Process Technology for Sub-50nm CMOS and Beyond(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices) Yoshitaka TSUNASHIMA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The noble process technology candidates to realize sub-50nm CMOS transistor are presented to overcome the issues that pointed out in ITRS roadmap. HfSiON high-k gate dielectric film was introduced in conventional poly-Si gate process integration, continuing to shrink down an equivalent oxide thickness (EOT) with reduced gate leakage current. Flash lamp annealing (FLA) technology could meet the target of ultra shallow junction requirements, such as depth, abruptness and resistance, to improve short channel effects. Damascene gate integration will not only allow an installation of new materials, high-k dielectric & metal gate, but also extend a flexibility of transistor engineering, such as recessed channel formation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-k gate dielectric / Ultra shallow junction / Flash lamp annealing / Damascene gate integration / Recessed channel transistor |
| Paper # | ED2003-63,SDM2003-74 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2003/6/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | [Invited]Front-End Process Technology for Sub-50nm CMOS and Beyond(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices) |
| Sub Title (in English) | |
| Keyword(1) | High-k gate dielectric |
| Keyword(2) | Ultra shallow junction |
| Keyword(3) | Flash lamp annealing |
| Keyword(4) | Damascene gate integration |
| Keyword(5) | Recessed channel transistor |
| 1st Author's Name | Yoshitaka TSUNASHIMA |
| 1st Author's Affiliation | Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation() |
| Date | 2003/6/23 |
| Paper # | ED2003-63,SDM2003-74 |
| Volume (vol) | vol.103 |
| Number (no) | 162 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |