| Presentation | 2003/1/31 Suppression of Stress Induced Open Failures between Via and Cu Wide Line by Inserting Ti Layer under Ta/TaN Barrier Makoto UEKI, Masayuki HIROI, Nobuyuki IKARASHI, Takahiro ONODERA, Naoya FURUTAKE, Masayuki YOSHIKI, Yoshihiro HAYASHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We verified the effect of Ti layer insertion on stress induced void formation in wide Cu lines where voids were formed under via. In order to improve adhesion property between via and underlying Cu, PVD-Ti was introduced under Ta/TaN barrier. When 8 nm thick PVD-Ti layer was inserted at via bottom, the failure was sufficiently suppressed without degrading the electromigration resistance. In addition, the via resistance was reduced by 25% compared with conventional Ta/TaN barrier structure, while the Cu metal resistivity was unchanged by the Ti insertion. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Stress induced void / Stress induced migration(SM) / adhesion / multi-level Cu interconnects / reliability / Cu-Ti alloy |
| Paper # | SDM2002-243 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2003/1/31(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Suppression of Stress Induced Open Failures between Via and Cu Wide Line by Inserting Ti Layer under Ta/TaN Barrier |
| Sub Title (in English) | |
| Keyword(1) | Stress induced void |
| Keyword(2) | Stress induced migration(SM) |
| Keyword(3) | adhesion |
| Keyword(4) | multi-level Cu interconnects |
| Keyword(5) | reliability |
| Keyword(6) | Cu-Ti alloy |
| 1st Author's Name | Makoto UEKI |
| 1st Author's Affiliation | Silicon System Research Labs., NEC Corporation() |
| 2nd Author's Name | Masayuki HIROI |
| 2nd Author's Affiliation | NEC Electronics Corporation |
| 3rd Author's Name | Nobuyuki IKARASHI |
| 3rd Author's Affiliation | Silicon System Research Labs., NEC Corporation |
| 4th Author's Name | Takahiro ONODERA |
| 4th Author's Affiliation | Silicon System Research Labs., NEC Corporation |
| 5th Author's Name | Naoya FURUTAKE |
| 5th Author's Affiliation | Silicon System Research Labs., NEC Corporation |
| 6th Author's Name | Masayuki YOSHIKI |
| 6th Author's Affiliation | Silicon System Research Labs., NEC Corporation |
| 7th Author's Name | Yoshihiro HAYASHI |
| 7th Author's Affiliation | Silicon System Research Labs., NEC Corporation |
| Date | 2003/1/31 |
| Paper # | SDM2002-243 |
| Volume (vol) | vol.102 |
| Number (no) | 637 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |