| Presentation | 2004/1/14 A Full-Rate-Clock 40-43Gb/s 16:1 Multiplexer and 1:16 Demultiplexer LSIs Akio KOYAMA, Tatsuhiro AIDA, Keiki WATANABE, Hiroki YAMASHITA, Nobuhiro SHIRAMIZU, CHIBA Hiroyuki /, Tsuyoshi TAKAHASHI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A chipset for 40-43Gb/s optical communication systems that function as 16:1 multiplexer (MUX) and 1:16 demultiplexer (DMUX) is developed using SiGe BiCMOS technology with 140GHz fT. This chipset employs a full-rate architecture with 40-43GHz clock distribution that contributes to suppressing jitter generation and realizing higher sensitivity. The 16 parallel interface operating at 2.5-2.7Gb/s is designed with implementation of industry standard OIF SFI-5 functionality to enhance the compatibility of this chipset with various types of Framers and FEC processors. The chipset is comprised of three LSIs, i.e., 16:1 MUX, 1:16 DMUX, and SFI-5, together with a pair of external 40GHz VCOs for MUX and DMUX. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Multiplexer / Demultiplexer / SerDes / 40Gb/s / Full-Rate-Clock / SiGe BiCMOS |
| Paper # | MW2003-248 |
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| Conference Information | |
| Committee | MW |
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| Conference Date | 2004/1/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Assistant | |
| Paper Information | |
| Registration To | Microwaves (MW) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Full-Rate-Clock 40-43Gb/s 16:1 Multiplexer and 1:16 Demultiplexer LSIs |
| Sub Title (in English) | |
| Keyword(1) | Multiplexer |
| Keyword(2) | Demultiplexer |
| Keyword(3) | SerDes |
| Keyword(4) | 40Gb/s |
| Keyword(5) | Full-Rate-Clock |
| Keyword(6) | SiGe BiCMOS |
| 1st Author's Name | Akio KOYAMA |
| 1st Author's Affiliation | Hitachi, Ltd., Device Development Center() |
| 2nd Author's Name | Tatsuhiro AIDA |
| 2nd Author's Affiliation | Hitachi, Ltd., Device Development Center |
| 3rd Author's Name | Keiki WATANABE |
| 3rd Author's Affiliation | Hitachi, Ltd., Device Development Center |
| 4th Author's Name | Hiroki YAMASHITA |
| 4th Author's Affiliation | Hitachi, Ltd., Central Research Laboratory |
| 5th Author's Name | Nobuhiro SHIRAMIZU |
| 5th Author's Affiliation | Hitachi, Ltd., Central Research Laboratory |
| 6th Author's Name | CHIBA Hiroyuki / |
| 6th Author's Affiliation | Hitachi, Ltd., Central Research Laboratory |
| 7th Author's Name | Tsuyoshi TAKAHASHI |
| 7th Author's Affiliation | Hitachi ULSI Systems Co., Ltd. |
| Date | 2004/1/14 |
| Paper # | MW2003-248 |
| Volume (vol) | vol.103 |
| Number (no) | 563 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |