| Presentation | 2004/7/25 Detailed Multi-Bank Register File Design for Superscalar Processors Moto MAEDA, Tetsuya SUEYOSHI, Kenichi AOYAMA, Tetsuo HIRONAKA, Tetsushi KOIDE, MATTAUSCH Hans JURGEN, Kazuya TANIGAWA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, the multi-port register file in the highly parallelized superscalar processors tends to have many ports, which causes problems with chip size, access time and power consumption. To solve this problem, we already have proposed the use of a multi-bank register file. In this paper, we show the structure of a superscalar processor with such a multi-bank register file. For the superscalar we designed the following units, the register access scheduling unit, the register renaming unit, and the reservation station, which support effective utilization of the multi-bank register file. By synthesising these units, we have in total of 55% larger number of gates as compared with the normal multi-port register file design. But the multi-bank register file achieves 70% smaller chip size, and the access cycle is improved by 32% in comparison to the conventional multi-port register file. From these results, we can say that our approach achieves small area and high performance. This paper shows the validity of using a multi-bank register file for a superscalar processors from the results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multi-bank register file register access scheduling |
| Paper # | CPSY2004-20 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2004/7/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Detailed Multi-Bank Register File Design for Superscalar Processors |
| Sub Title (in English) | |
| Keyword(1) | multi-bank register file register access scheduling |
| 1st Author's Name | Moto MAEDA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Tetsuya SUEYOSHI |
| 2nd Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 3rd Author's Name | Kenichi AOYAMA |
| 3rd Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 4th Author's Name | Tetsuo HIRONAKA |
| 4th Author's Affiliation | Department of Computer Engineering, Hiroshima City University |
| 5th Author's Name | Tetsushi KOIDE |
| 5th Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 6th Author's Name | MATTAUSCH Hans JURGEN |
| 6th Author's Affiliation | Research Center for Nanodevices and Systems, Hiroshima University |
| 7th Author's Name | Kazuya TANIGAWA |
| 7th Author's Affiliation | Department of Computer Engineering, Hiroshima City University |
| Date | 2004/7/25 |
| Paper # | CPSY2004-20 |
| Volume (vol) | vol.104 |
| Number (no) | 241 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |