Presentation 2004/3/11
The architecture of multi-threaded processor for stream signal processing
Shin-ichi KANNO, Masaya TARUI, Taku OHNEDA, Riku OGAWA, Yukimasa MIYAMOTO,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this paper, we propose the multi-threaded processor architecture for stream signal processing. It schedules based on FIFO's which connect between thread to thread. We estimate the performance of this architecture in some of typical application. It perform reduce performance loss caused context switch.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Software Defined Radio / Multi-thread
Paper # CPSY2003-48
Date of Issue

Conference Information
Committee CPSY
Conference Date 2004/3/11(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) The architecture of multi-threaded processor for stream signal processing
Sub Title (in English)
Keyword(1) Software Defined Radio
Keyword(2) Multi-thread
1st Author's Name Shin-ichi KANNO
1st Author's Affiliation Corporate Reserch and Development Center, TOSHIBA Corporation()
2nd Author's Name Masaya TARUI
2nd Author's Affiliation Corporate Reserch and Development Center, TOSHIBA Corporation
3rd Author's Name Taku OHNEDA
3rd Author's Affiliation Corporate Reserch and Development Center, TOSHIBA Corporation
4th Author's Name Riku OGAWA
4th Author's Affiliation Corporate Reserch and Development Center, TOSHIBA Corporation
5th Author's Name Yukimasa MIYAMOTO
5th Author's Affiliation Corporate Reserch and Development Center, TOSHIBA Corporation
Date 2004/3/11
Paper # CPSY2003-48
Volume (vol) vol.103
Number (no) 735
Page pp.pp.-
#Pages 6
Date of Issue