| Presentation | 2004/3/11 Instruction Supply Mechanism For Real-time Systems of Responsive Multithreaded Processor Hiroyuki USUI, Masato UCHIYAMA, Tsutomu ITO, Nobuyuki YAMASAKI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We design and implement the instruction supply mechanism for Responsive Multithreaded Processing Unit (RMT PU), which is a processing unit of Responsive Multithreaded Processor for distributed real-time systems. In RMT PU, priority of a real-time system is used for solution to the competition of all functional units of the 8way Simultaneous Multithreading(SMT), and it performs SMT execution giving priority to high priority threads. By handling threads without context switching and increasing the utilization of a processor, the schedulability is improved rather than conventional systems. RMT PU can execute threads only by hardware, when the number of threads is less than or equal to 8 and static scheduling is used. Furthermore, in order to cope with more threads and dynamic scheduling, it has the on-chip context caches for 32 thread contexts, and the overhead of context switching is reduced sharply by switching context by hardware. According to these features, the real-time execution of both soft real-time and hard real-time is supported by hardware, and the real-time execution with a shorter quantum time can be achieved. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Real-time Systems / Processor Architecture / Embedded Systems / Multithread |
| Paper # | CPSY2003-47 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2004/3/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Instruction Supply Mechanism For Real-time Systems of Responsive Multithreaded Processor |
| Sub Title (in English) | |
| Keyword(1) | Real-time Systems |
| Keyword(2) | Processor Architecture |
| Keyword(3) | Embedded Systems |
| Keyword(4) | Multithread |
| 1st Author's Name | Hiroyuki USUI |
| 1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
| 2nd Author's Name | Masato UCHIYAMA |
| 2nd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 3rd Author's Name | Tsutomu ITO |
| 3rd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 4th Author's Name | Nobuyuki YAMASAKI |
| 4th Author's Affiliation | Faculty of Science and Technology, Keio University |
| Date | 2004/3/11 |
| Paper # | CPSY2003-47 |
| Volume (vol) | vol.103 |
| Number (no) | 735 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |