| Presentation | 2003/1/22 A Fast Redundant Binary Multiplier Excluding the Intermediate Sum Operation of Redundant Binary Adders Tsunetomo NAKAZATO, Hiroyuki SHIMAJIRI, Takeo YOSHIDA, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Accelerating methods that use a redundant binary representation for multipliers are good for VLSI implementation and have been concentrated lately. We examine an accelerating method for redundant binary multipliers using second order Booth's method. At a redundant binary multiplier which Booth's method is applied to, partial products are generated by every two digit of a multiplier and are accumulated. In this paper, we consider a redundant binary representation that makes additions of partial products fast, in order to accelerate a redundant binary multiplier which Booth's method is applied to. We evaluate1 delay time and circuit area of proposed redundant binary array multiplier. As a result, delay time and circuit area are reduced about 53% and 56%, respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Redundant Binary Representation / Redundant Binary Multiplier / Booth's Method / Partial Product / Intermediate Sum Operation |
| Paper # | CPSY2002-84 |
| Date of Issue |
| Conference Information | |
| Committee | CPSY |
|---|---|
| Conference Date | 2003/1/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Computer Systems (CPSY) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Fast Redundant Binary Multiplier Excluding the Intermediate Sum Operation of Redundant Binary Adders |
| Sub Title (in English) | |
| Keyword(1) | Redundant Binary Representation |
| Keyword(2) | Redundant Binary Multiplier |
| Keyword(3) | Booth's Method |
| Keyword(4) | Partial Product |
| Keyword(5) | Intermediate Sum Operation |
| 1st Author's Name | Tsunetomo NAKAZATO |
| 1st Author's Affiliation | Department of Information Engineering, University of the Ryukyus.() |
| 2nd Author's Name | Hiroyuki SHIMAJIRI |
| 2nd Author's Affiliation | Department of Information Engineering, University of the Ryukyus. |
| 3rd Author's Name | Takeo YOSHIDA |
| 3rd Author's Affiliation | Department of Information Engineering, University of the Ryukyus. |
| Date | 2003/1/22 |
| Paper # | CPSY2002-84 |
| Volume (vol) | vol.102 |
| Number (no) | 611 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |