Presentation	2003/1/21 A Verification Method for System On a Chip by using Combined Approach of FPGA Emulation and PC Software Yuichi Nakamura, Kouhei Hosokawa,
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Abstract(in English)	This paper describes a new verification method for Systems On a Chip. The proposed method integrates FPGA based modeling using an emulation engine and software based modeling on a PC. The communication between the FPGA emulation and the PC is implemented by simple bus architecture. The proposed method achieves low cost, easy debugging, rich portability, and high verification speed. For a cheap verification environment, it must be implemented by at least the number of FPGAs. The method was applied to 3 verification projects involving the design of real chips. In these projects, this verification methodology completes system verification at 0.5-16MHz using at most 3 FPGAs and a Windows PC.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	SoC / System Verification / FPGA
Paper #	CPSY2002-77
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Conference Information
Committee	CPSY
Conference Date	2003/1/21(1days)
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Paper Information
Registration To	Computer Systems (CPSY)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Verification Method for System On a Chip by using Combined Approach of FPGA Emulation and PC Software
Sub Title (in English)
Keyword(1)	SoC
Keyword(2)	System Verification
Keyword(3)	FPGA
1st Author's Name	Yuichi Nakamura
1st Author's Affiliation	Multimedia Laboratories, NEC Corporation()
2nd Author's Name	Kouhei Hosokawa
2nd Author's Affiliation	Multimedia Laboratories, NEC Corporation
Date	2003/1/21
Paper #	CPSY2002-77
Volume (vol)	vol.102
Number (no)	610
Page	pp.pp.-
#Pages	6
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