| Presentation | 2003/11/28 Slot-line model for the slit on a ground plane and its limitation Hiroshi HIRAYAMA, Yoshio KAMI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Interconnections of Printed-Circuit Board (PCB) and boundaries between different voltage power planes are treated as slit on a ground plane. A signal integrity of a transmission line crossing on the slit is becoming a problem. In this report, we show that the signal integrity can be expressed with a model of the slit by using slot line. Experiments examines this effects and limitations. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Signal Integrity / Slot-line model / Time-domain waveform measurement |
| Paper # | EMCJ2003-118 |
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| Conference Information | |
| Committee | EMCJ |
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| Conference Date | 2003/11/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Electromagnetic Compatibility (EMCJ) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Slot-line model for the slit on a ground plane and its limitation |
| Sub Title (in English) | |
| Keyword(1) | Signal Integrity |
| Keyword(2) | Slot-line model |
| Keyword(3) | Time-domain waveform measurement |
| 1st Author's Name | Hiroshi HIRAYAMA |
| 1st Author's Affiliation | Department of Electric and Computer Engineering Nagoya Institute of Technology() |
| 2nd Author's Name | Yoshio KAMI |
| 2nd Author's Affiliation | Department of Information and Communication Engineering University of Electro-Communications |
| Date | 2003/11/28 |
| Paper # | EMCJ2003-118 |
| Volume (vol) | vol.103 |
| Number (no) | 488 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |