| Presentation | 2004/1/16 Hardware Implementation of Invertible Deinterlacing with Horizontal Decimation of Coefficient Parameters Tatsuumi SOYAMA, Jun UCHITA, Takuma ISHIDA, Shogo MURAMATSU, Hisakazu KIKUCHI, Tetsuro KUGE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this report, an architecture of invertible deinterlacing with horizontal decimation of coefficient-parameter is proposed. Invertible deinterlacing can be used for interlaced video as preprocessing of frame-based motion picture codec, such as Motion-JPEG2000 (MJP2). When simple field-interleaving is used, comb-tooth artifacts may appear around edges of motion objects. In contrast, invertible deinterlacing technique can suppress comb-tooth artifacts and also guaranties original picture recovery on demand. In previous work, we have developed a variable coefficient scheme with a motion detection filter, which realizes adaptability to local characteristics of pictures. When the scheme is applied to an image codec, it is necessary to send the coefficient parameters to receivers to recover the original image. Before we have shown that the coefficient parameters can be reduced by horizontally decimating while maintaining the comb-tooth suppression ability. This report shows that an architecture of our proposed parameter decimation approach, of which performance is also evaluated by using VHDL models. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Invertible deinterlacing / Intraframe-based coding / Scalable coding / Variable coefficients / Motion-JPEG2000 / Hardware architecture |
| Paper # | CAS2003-105 |
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| Committee | CAS |
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| Conference Date | 2004/1/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Implementation of Invertible Deinterlacing with Horizontal Decimation of Coefficient Parameters |
| Sub Title (in English) | |
| Keyword(1) | Invertible deinterlacing |
| Keyword(2) | Intraframe-based coding |
| Keyword(3) | Scalable coding |
| Keyword(4) | Variable coefficients |
| Keyword(5) | Motion-JPEG2000 |
| Keyword(6) | Hardware architecture |
| 1st Author's Name | Tatsuumi SOYAMA |
| 1st Author's Affiliation | Faculty of Engineering, Niigata University() |
| 2nd Author's Name | Jun UCHITA |
| 2nd Author's Affiliation | Faculty of Engineering, Niigata University |
| 3rd Author's Name | Takuma ISHIDA |
| 3rd Author's Affiliation | Faculty of Engineering, Niigata University |
| 4th Author's Name | Shogo MURAMATSU |
| 4th Author's Affiliation | Faculty of Engineering, Niigata University |
| 5th Author's Name | Hisakazu KIKUCHI |
| 5th Author's Affiliation | Faculty of Engineering, Niigata University |
| 6th Author's Name | Tetsuro KUGE |
| 6th Author's Affiliation | Science & Technical Research Laboratories, NHK |
| Date | 2004/1/16 |
| Paper # | CAS2003-105 |
| Volume (vol) | vol.103 |
| Number (no) | 569 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |