| Presentation | 2004/1/16 Design of Sound Localization LSI based on Pulse Neuron Model using Sigma-Delta Modulation Takahiro YOSHINO, Eisuke ARAI, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In past, the sound localization system using the pulse neuron model emulating the behavior of nerve cell "neuron" was proposed and the hardware implementation was examined. In the present work, we have investigated the neuron circuit in the modified model by using sigma-delta modulation which is used for analog circuit implementation. For the sound localization system implemented on hardware, many neuron circuits will be involved in the system in order to take advantage of high speed processing by parallel operation of each neuron circuit. Therefore, it is highly desirable that the neuron circuit operates with as low power consumprion as possible. Consequently, we propose the level shift circuit without bias current which can considerably reduce the power consumption when emulating the fire of neuron. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | sound localization / auditory nerve / pulse neuron / sigma-delta modulation |
| Paper # | CAS2003-102 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2004/1/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Sound Localization LSI based on Pulse Neuron Model using Sigma-Delta Modulation |
| Sub Title (in English) | |
| Keyword(1) | sound localization |
| Keyword(2) | auditory nerve |
| Keyword(3) | pulse neuron |
| Keyword(4) | sigma-delta modulation |
| 1st Author's Name | Takahiro YOSHINO |
| 1st Author's Affiliation | Department of Electrical and Computer Engineering. Nagoya Institute of Technology() |
| 2nd Author's Name | Eisuke ARAI |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering. Nagoya Institute of Technology |
| Date | 2004/1/16 |
| Paper # | CAS2003-102 |
| Volume (vol) | vol.103 |
| Number (no) | 569 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |