Presentation | 2003/10/31 Implementation of a Hardware for Matrix Calculation on FPGA Wei CUI, Cong-Kha PHAM, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In the scientific calculation such as quantum mechanics, it takes an enormous computational complexity, which is proportionated by 3 power of the degree of queue N. In other words, if the degree of queue is lager than 1000, then it will require in several hours or more for calculation using PC. In our work, to solve the problem memtioned above, we propose a special purpose hardware to reduce the calculation time. VHDL has been used to design the fuction of the hardware and implemented using FPGA. As a result, a shorter calculation time is obtained using the proposed hardware. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FPGA / VHDL / Matrix calculation hardware |
Paper # | CAS2003-83,CST2003-26 |
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Conference Information | |
Committee | CAS |
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Conference Date | 2003/10/31(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Circuits and Systems (CAS) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Implementation of a Hardware for Matrix Calculation on FPGA |
Sub Title (in English) | |
Keyword(1) | FPGA |
Keyword(2) | VHDL |
Keyword(3) | Matrix calculation hardware |
1st Author's Name | Wei CUI |
1st Author's Affiliation | Graduate School of Electro-Communications, University of Electro-Communications() |
2nd Author's Name | Cong-Kha PHAM |
2nd Author's Affiliation | Graduate School of Electro-Communications, University of Electro-Communications |
Date | 2003/10/31 |
Paper # | CAS2003-83,CST2003-26 |
Volume (vol) | vol.103 |
Number (no) | 404 |
Page | pp.pp.- |
#Pages | 4 |
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