Presentation | 2003/1/15 Research on a Parallel Method for the MOSFET Model in Circuit Simulation Yuichiro HATANO, Yasuyoshi HORIBATA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This research describes a parallel method in order to improve the simulation speed in the large-scale integrated circuit. In simulation SPICE2, which is one of the standard circuit simulators, the device model evaluation takes the most processing time. Thus we develop a parallel method for it. The parallel method is applied to the MOSFET models using SMP-Cluster, in which the distributed memory system and the shared memory system are mixed. An experimental result is presented for a benchmark circuit of 1-128 bit adder circuit. The simulation speeds have become 1.7 times as fast as that for SPICE2. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Circuit Simulation / device model evaluation / Parallel processing / PC-Cluster system / Multi-thread |
Paper # | CAS2002-115 |
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Committee | CAS |
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Conference Date | 2003/1/15(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Circuits and Systems (CAS) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Research on a Parallel Method for the MOSFET Model in Circuit Simulation |
Sub Title (in English) | |
Keyword(1) | Circuit Simulation |
Keyword(2) | device model evaluation |
Keyword(3) | Parallel processing |
Keyword(4) | PC-Cluster system |
Keyword(5) | Multi-thread |
1st Author's Name | Yuichiro HATANO |
1st Author's Affiliation | Graduate Course of Engineering,Hosei University() |
2nd Author's Name | Yasuyoshi HORIBATA |
2nd Author's Affiliation | Graduate Course of Engineering,Hosei University |
Date | 2003/1/15 |
Paper # | CAS2002-115 |
Volume (vol) | vol.102 |
Number (no) | 572 |
Page | pp.pp.- |
#Pages | 5 |
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