Presentation 2002/6/20
Design of VLSI-Oriented Redundant Addition Algorithms Using CTDs
Jun SAKIYAMA, Takafumi AOKI, Tatsuo HIGUCHI,
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Abstract(in English) This paper presents Counter Tree Diagrams (CTDs) for designing redundant addition algorithms. By using CTDs, one can describe and analyze arbitrary adder architectures in a systematic way without using specific knowledge about underlying arithmetic algorithms. Examples of adder architectures considered in this paper include Redundant-Binary (RB) adders, Signed-Digit (SD) adders, Positive-Digit (PD) adders, parallel counters (e.g., 3-2 counters and 4-2 counters) and networks of such basic adders/counters. This paper also presents an application of CTDs to the design of fast adders with limited carry propagation.
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Keyword(in English) redundant adders / multipliers / parallel counters / arithmetic algorithms / VLSI
Paper # CAS2002-24
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Committee CAS
Conference Date 2002/6/20(1days)
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Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design of VLSI-Oriented Redundant Addition Algorithms Using CTDs
Sub Title (in English)
Keyword(1) redundant adders
Keyword(2) multipliers
Keyword(3) parallel counters
Keyword(4) arithmetic algorithms
Keyword(5) VLSI
1st Author's Name Jun SAKIYAMA
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Takafumi AOKI
2nd Author's Affiliation Graduate School of Information Sciences, Tohoku University
3rd Author's Name Tatsuo HIGUCHI
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 2002/6/20
Paper # CAS2002-24
Volume (vol) vol.102
Number (no) 161
Page pp.pp.-
#Pages 6
Date of Issue